A Mach-Zehnder Modulator (MZM) splits a received optical input (e.g., optical signal) into portions. One portion is provided to a first arm (e.g., waveguide) while the other portion is provided to a second arm. Phase change is applied to the optical signal portion propagating through one or both arms such that when the optical signal portions are later recombined, either constructive or destructive interference occurs. The phase change applied to the optical signal portions is a function of an electrical input voltage provided by an electronic driver circuit coupled to the MZM.
A segmented MZM contains multiple electrical inputs applied along one or both of the arms. Each electrical input is supplied with an electrical input voltage by the electronic driver circuit. A major challenge in designing a segmented MZM is ensuring that electrical signals received from the electronic driver circuit and optical signals propagating through the arms are aligned given that their respective velocities are different. This is readily apparent when comparing the optical index of a silicon waveguide, which is 4, to the electrical index of a silicon dioxide interlayer dielectric, which is 2. Because the electrical signal is faster than the optical signal, a common approach is to insert additional delay into the electronic driver circuit.
One known method to introduce delay into the electronic driver circuit is to use transmission lines. Transmission lines offer very accurate delay with precise delay control, but they have a number of drawbacks. For example, transmission lines require controlled impedance design and are prone to cross-talk. In addition, the routing of transmission lines requires complicated meandering. As a result, transmission line patterns are large, which may directly translate into higher cost. Further, transmission lines need higher power amplifiers, typically implementing analog-based topologies, to drive and receive.
In addition, buffer stages are usually implemented to drive large capacitive loads, and hence they normally have gate widths that increase in size with each additional stage. However, implementing delay buffer stages with increasingly fanned-out widths results in large delays on the order of 20 picoseconds (ps) and correspondingly poor precision on the order of 10 ps over process/voltage/temperature (PVT) corners. For silicon photonic applications, the amount of delay desired falls into an awkward region of being too small to achieve using normal active delay techniques and too large to achieve passively without considering transmission line effects. Therefore, a major problem is how to achieve an active delay that is much smaller than is normally available.